(1) Field of the Invention
The present invention relates to a frame synchronous pattern processing apparatus and a frame synchronous pattern detection apparatus and a method for detecting frame synchronous pattern, and more particularly to the frame synchronous pattern processing apparatus and frame synchronous pattern detection apparatus and the method for detecting frame synchronous pattern which may be used advantageously for the synchronized digital signal transmission network including SDH (Synchronous Digital Hierarchy) or SONET (Synchronous Optical Network).
(2) Description of the Related Art
(A) Brief Description of SDH Transmission System
As it is well known, for the realization of B-ISDN, ITU-T is now standardizing SDH as an internationally however unified digital hierarchy (however, North America standardizes the above-mentioned SONET as its original hierarchy).
This SDH (or SONET) adopts a multiplexing method for multiplexing by adding an overhead containing information for maintenance and operation to a plurality of signals of lower group level and, therefore, the multiplexed frame comprises a format including a plenty of maintenance and operation information for respective speed as described in the item (B) below.
The overhead includes, normally, section overhead (SOH) for transmission line and path overhead (POH) for path, for multiplexing generally by adding POH to signal of lower group side (lower group level) and finally SOH is added.
(B) Description of SDH (SONET) Transmission Network
FIG. 40 is a block diagram showing an example of SDH (SONET) transmission network and, in this FIG. 40, 301 indicates subscriber terminal, 302 line terminal apparatus (NT), 303 and 306 transmission terminal station equipment (LT) respectively, 304 switch gear (SW), 305 multiplexer (MUX) and 307 relay transmission line.
In SDH (SONET) transmission network shown in this FIG. 40, lower group level data from a plurality of subscriber terminals 301 is byte multiplexed in the multiplexer 305 to be stacked into STM-N (STS-M) frame (wherein N and M represent multiplexing factor and N=1, 4, 16, 64, . . . : M=3, 12, 48, 192, . . . ), processed by overhead (SOH, POH) termination/replacement processing or AU/TU pointer termination/replacement processing in the transmission terminal station apparatus 306 before being transmitted through the relay transmission line 307 to the corresponding subscriber terminal 301 side.
By the way, STM-1 (STS-3) frame constituting the basic multiplexed frame in the SDH (SONET) includes, as shown in FIG. 41, a format represented by two-dimensional byte array of 9 rows×270 bytes wherein the leading 9 rows×9 bytes are composed of a section overhead (SOH) 231 and AU (AU-4) pointer 232 and the following 9 rows×261 bytes are called payload (SPE: Synchronous Payload Envelope) 233 containing multiplexed information (VC: lower group level data).
Moreover, the section overhead 231 includes, as shown in FIG. 42, basically, a relay section overhead (RSOH: Regenerator-SOH) 231A and a terminal station section overhead (MSOH: Multiplex-SOH) 231 B. The relay section overhead 231 A is used for signal maintenance/operation in the relay section [mutually between repeaters (existing on the relay transmission line 307: not illustrated) and between the repeater and the transmission terminal station apparatus 306] and composed of a frame synchronous pattern (A1, A2 byte) and B1 byte for coding error monitoring in the relay section and the like.
On the other hand, the terminal station section overhead 231 B is used for signal maintenance/operation in the terminal station section (between transmission terminal station apparatuses 306), and composed of B2 byte for coding error monitoring in the terminal station section and of K1, K2 byte [APS (Automatic Protection Switch) byte] used for supplying/receiving signal for controlling a system switching between the transmission terminal station apparatuses 306 and used for a display of an in alarm state in respect of the trouble of the repeaters and the relay transmission line 307.
AU4 pointer 232 is used for indicating a containing position (frame leading position) of VC(VC4) in the payload 233 and composed of H1–H3 bytes, and these H1–H3 bytes are used for the pointer value updating or the phase adjustment in clock switching (positive staff/negative staff) or the like.
Here, in FIG. 42, two bytes marked by * and X following C1 byte are respectively bytes not scrambled upon the transmission, each byte marked by X is respectively reserved for domestic use and each blank byte is reserved for future international standardization.
STM-4 (STS-12) frame is built up by byte multiplexing 4 frames (in the multiplexer 305) of STM-1 (STS-3) comprising the above-mentioned format, then, STM-16 (STS-48) is built up by byte multiplexing 4 frames of STM-4 (STS-12) and similarly STM-N (STS-M) frame is built up sequentially by byte multiplexing lower group side frames by 4 frames.
In consequence, for instance, the section overhead 231 of an STM-4 frame is composed of, as shown in FIG. 43, 9 rows×144 bytes wherein section overhead 231 shown in FIG. 42 is byte multiplexed by four and the section overhead 231 of STM-64 (STS-192) frame is composed of 9 rows×576 bytes.
Next, FIG. 44 is a block diagram showing the composition example of the essential part of the transmission terminal station apparatus 306. As shown in this FIG. 44, the transmission terminal station apparatus 306 comprises a current system 403A and a standby system 403B including respectively, for instance, a SOH termination processing section 404, an AU pointer processing section 405, a TU pointer processing section 406, an elastic memory (ES) section 407, a POH termination processing section (POH termination processor) 408 and a path switch alarm insertion section 409. 410 indicates a microcomputer (μ-COM) and 411 a cross connect apparatus (XC).
Here, the SOH termination processing section 404 executes an SOH termination processing such as a frame synchronization establishment, a coding error monitoring and so on based on the section overhead 231 of a received multiplexed frame (STM-N/STS-M), and the AU pointer processing section 405 extracts a TU signal by recognizing the frame leading position of TU level contained in the payload 233 based on the AU pointer 232 included in the AU4 signal removed of RSOH231A and MSOH231B by the termination processing.
The TU pointer processing section 406, extracts a signal of VC level contained in the TU signal (decomposition of the TU signal into a VC signal) based on the TU pointer included in the TU signal extracted in the AU pointer processing section 405, the ES section 407 executes clock switching process of the VC signal and the POH termination processing section 408 performs, through the monitoring of the path overhead which is the overhead of the VC signal, a BIP (Bit Interleaved Parity) operation or a UNEQ (Unequipped: indicates that VC signal does not contain the payload 233) alarm detection and other.
The path switch alarm insertion section 409 inserts a path switch alarm as a control information for indicating the switching process of current system 403A/standby system 403B to the VC signal according to the setting by the microcomputer 410.
Thus, in the transmission termination apparatus 306, first, in the SOH termination processing section 404, the frame synchronization is established by detecting the frame synchronous pattern through the detection of a given bit pattern of A1, A2 byte contained in the section overhead 231 of the received multiplexed frame, the BIP operation in respect of B1 byte or other various types of termination processing are performed to break down the received multiplexed frame into the AU4 signal.
Next, the AU4 signal is broken down into the TU signal based on the AU4 pointer 232 in the TU pointer processing section 406, and moreover this TU signal is broken down into the VC signal based on the TU pointer in the TU pointer processing section 406. The thus obtained VC signal is clock-changed over from the transmission line side clock to the apparatus side clock in the ES section 407 so that the transmission speed can be processed in the following stage.
Here, the POH termination processing section 408 executes the necessary termination processing such as the coding error monitoring or the alarm display to the path overhead contained in the VC signal. When any alarm is detected in this termination processing, an alarm processing according to the detected alarm will be performed by the path switch alarm insertion section 409 and the microcomputer 410.
For instance, if an UNEQ alarm is detected in this POH termination processing section 408, this UNEQ alarm is supplied to the path switch alarm insertion section 409 and, the BIP operation result (BIPPM: BIP performance monitor) is notified to the microcomputer 410. Being notified, the microcomputer 410 executes an alarm processing by software before setting the path switch alarm insertion to the path switch alarm insertion section 409 (the signal of the TU channel which has detected the UNEQ alarm is set to ALL 1).
In the cross connect apparatus (XC) 11, if an anomaly is detected by the detection of the TU channel set to the ALL “1”, the transmission system of that channel shall be switched from the current system 3A to the standby channel 3B.
Thus, in the transmission terminal station apparatus 306, after the frame synchronization is established by executing SOH termination processing to the received multiplexed frame, the AU pointer processing and the POH termination processing or other, are sequentially executed under the condition wherein the frame synchronization is established. As a result, the transmission terminal station apparatus 306 can break down the received multiplexed frame into the VC signal and can execute the alarm detection process precisely during this breaking-down process.
By the way, in the SOH termination processing section 404, when the multiplexing factor n of the multiplexed frame increases and the data transmission rate achieves higher rate such as 115 Mbps (STM-1/STS-3), 622 Mbps (STM-4/STS-12), 2.4 Gbps (STM-16/STS-48), 10 Gbps (STM-64/STS-192), the device operation rate, power consumption or other problems occur, so the establishment of a setup/hold margin or the lower power consumption are assured reducing the rate by converting once the multiplexed frame (multiplexed serial data) into parallel data.
However, in this case, as A1, A2 bytes of the number corresponding to the multiplexed frame multiplexing factor N (M) exist (by 3×N for STM-N and by M for STS-M) in the section overhead 231 of the multiplexed frame as shown in FIG. 42 and FIG. 43, if the multiplexed frame is paralleled by m [in which m=8(bit)×natural number], as shown in FIG. 45, for example, m positions of the leading position of A1(A2) bytes exist in m parallel data, namely m patterns of the frame synchronous pattern (FDET) to be detected exist.
As the consequence, in the SOH termination processing section 404, m ways of detection of A1, A2 byte (frame synchronous pattern) shall be executed in accordance with the parallel factor m of the multiplexed frame.
FIG. 46 is a block diagram showing the composition of the SOH termination processing section 404 in respect of such frame synchronous pattern detection function and, as shown in this FIG. 46, the SOH termination processing section (frame synchronous pattern processing apparatus) 404 comprises a serial/parallel (S/P) conversion section 412, a byte switch (BSW) section 413, a frame synchronous pattern detection (FDET) section 414-1 to 414-m, a counter control section 415, a frame counter 416, a synchronization protection section 417 and a byte switch control section 418.
Here, the S/P conversion section 412 S/P converts the received multiplexed serial data (received multiplexed frame) into m parallel data and the byte switch section 413 performs the slot replacement (data rearrangement) so that the frame synchronous pattern (A1, A2 byte) in m parallel data is positioned at the leading slot under the control of the byte switch control section 418. It should be noted that this slot rearrangement is performed so as to proceed to the replacement of the section overhead 231 which is performed sequentially from the leading slot in the following stage.
On the other hand, respective frame synchronization detection section (frame synchronous pattern detection apparatus) 414-1 to 414-m detects respectively A1, A2 byte (given bit pattern) from the m parallel data and, in this case, the leading slot position of the A1 (A2) byte exists m ways in the m parallel data (namely m× frame synchronous pattern to be detected exist) so m sections are provided as shown in FIG. 46.
Moreover, the counter control section 415 controls the counting operation of the frame counter 416 and, for example, the count value of the frame counter 416 is counted up each time a frame synchronous pattern is detected in the frame synchronous pattern detection section 414-i (in which i=1 to m) and the count value of the frame counter 416 is reset on the reception of the synchronization establishment signal (OOF) described below from the synchronization protection section 416.
Additionally, the frame counter 416 counts the count value corresponding to the given protection stages under the control of the counter control section 415 and when the count value of the frame counter 416 attains a given value (number of protection stages), the synchronization protection section 417 outputs the synchronization establishment signal (OOF) indicating the establishment of frame synchronization by a consecutive detection of the frame synchronous pattern in the frame synchronous pattern detection section 414-i in a given number of times.
Receiving the synchronization establishment signal (OOF) from the synchronization protection section 417, the byte switch control section 418 performs the slot rearrangement processing by controlling the byte switch 413 so that the leading one of the frame synchronous patterns detected at that moment by the frame synchronous pattern detection section 414-i is positioned at the leading slot in m parallel data.
Given such composition, in the SOH termination processing section 404, first, the received multiplexed serial data is converted into low speed parallel data through m parallelization by the S/P converter 412 before detecting A1, A2 byte (predetermined bit pattern of 16 bits in total) contained in this m parallel data by the frame synchronous pattern detection section 414-i for detecting the frame synchronous pattern.
When it is recognized that the frame synchronous pattern is detected in the given times consecutively through the counter control section 415, the frame counter 416 and the synchronization protection section 417, the byte switch 413 and the byte switch control section 418 rearrange slots so that the leading position of such frame synchronous pattern is placed at the leading slot in m parallel data.
Thus, concerning main signal data for the following stage, as the frame synchronous pattern is always positioned at its leading slot, data may only be inserted sequentially from the leading slot for changing the section overhead 231.
However, as in the SOH termination processing section (frame synchronous pattern processor) 404 the frame synchronous pattern existing in m ways in m parallelized parallel data is detected by the frame synchronous pattern detection section 414-i, the frame pattern detection circuit which was necessary only by one way for the entire apparatus in the serial data processing (refer to FIG. 47) will be necessary by m ways for the entire apparatus (refer to FIG. 48), according to the increase of the multiplexed factor of the multiplexed frame (increase of parallel processing rate), the number of equipment gate and the number of inner net increases so as to increase bulk size and cost of LSI, the layout will be complex and other problems will appear.
Moreover, as the frame synchronous pattern detection signals are produced m ways by the frame synchronous pattern detection section 414-i, the control of the frame counter 416, the synchronization protection section 417 or the byte switch control section 418 will be complex so as to provoke LSI bulk size, layout and cost problem in the same way.